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Title page for ETD etd-12092014-230739

Type of Document Dissertation
Author Mahatme, Nihaar Nilesh
Author's Email Address nihaar.n.mahatme@vanderbilt.edu
URN etd-12092014-230739
Title Design Techniques for Power-Aware Combinational Logic SER Mitigation
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Bharat Bhuva Committee Chair
Anthony Oates Committee Member
Lloyd Massengill Committee Member
Robert Reed Committee Member
Ronald Schrimpf Committee Member
  • combinational logic
  • circuit reliability
  • soft errors
Date of Defense 2014-08-01
Availability unrestricted
Ensuring low power operation is a major challenge for designers in the era of portable devices, cloud computing and networked sensor systems. Concomitantly, combinational logic soft errors caused by radiation particle strikes have emerged as a major reliability-limiting problem for integrated circuits. However, most approaches that mitigate combinational logic soft errors lead to significant power overheads. This work explores techniques to jointly reduce the power consumption as well as mitigate combinational logic soft errors. At the circuit level, this is achieved by redesigning circuits in a way that reduces the number of switching nodes and reduces the effective area of the circuit that is sensitive to radiation particle strikes. At the architectural level, pipelining is used as a tool to lower power consumption and improve the combinational logic soft error reliability. Thus, optimization for power and soft error reliability is performed at various levels of design abstraction and the benefit of cross-layer optimization is identified. Additionally, the impact of technology scaling on the combinational logic soft error rate is identified experimentally and predictions for future technology generations are made.
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