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Title page for ETD etd-12022009-131433

Type of Document Master's Thesis
Author Reece, Trey
URN etd-12022009-131433
Title Detection of Malicious Hardware in ASICs and FPGAs
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Bharat L. Bhuva Committee Member
William H. Robinson Committee Member
  • Malicious Hardware
  • Process variation
  • hardware trojan
Date of Defense 2009-12-03
Availability unrestricted
Detecting malicious modifications to a circuit is a daunting task, regardless of the medium. In a fabricated circuit, most methods of detecting hardware Trojans rely on small changes in side-channel measurements, which can easily be disturbed by the presence of severe process variation. In a Field Programmable Gate Array (FPGA), the reprogrammability and design transparency reduces the initial difficulty of inserting a Trojan to a circuit. This thesis suggests solutions for both situations. The first method uses a signature generated from altering the supply voltage to the circuit in a controlled manner; this process leads to a change in shape of the transient current response of the integrated circuit (IC). Simulation results presented show significant differences between circuits with and without malicious hardware (i.e., Trojans), despite large variations in individual transistor parameters. Second is a Trojan-protection by design method where a controllable ring-oscillator is inserted into a circuit in order to detect modifications that change the timing of its component gates. This design was able to win 2nd place in a competition held by the Polytechnic Institute of New York University.
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