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Title page for ETD etd-11142004-232600

Type of Document Dissertation
Author Xiong, Hao D.
Author's Email Address hao.xiong@vanderbilt.edu
URN etd-11142004-232600
Title Low frequency noise and charge trapping in MOSFETs
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Dan Fleetwood Committee Chair
Robert Weller Committee Member
Ron Schrimpf Committee Member
Sokrates Pantelides Committee Member
Tim Holman Committee Member
  • charge trapping
  • SOI buried oxide
  • radiation effects
  • 1/f noise
Date of Defense 2004-11-01
Availability unrestricted
We have studied 1/f noise and total-dose response associated with Al2O3/SiOxNy/Si(100) gate dielectrics. Both the radiation-induced threshold-voltage shifts and the low-frequency noise are significantly larger than are typically observed for high-quality thermal SiO2 thin films of comparable thicknesses.

Charge trapping effects and low frequency noise are studied in the buried oxides of fully depleted nMOS SOI transistors. Silicon implantation in the buried oxide creates a higher density of oxygen vacancy-related defects that reduce the net oxide-trap charge, but increase the back-channel 1/f noise. The 1/f noise of MOSFETs fabricated on silicon-implanted SOI buried oxides shows little change after 1 Mrad(SiO2) irradiation. The temperature and frequency dependences of the 1/f noise of back channel SOI nMOS transistors shows thermally-activated charge exchange between the Si channel and defects in the buried oxide. Silicon implantation also creates shallow electron traps in the buried oxide, leading to large bias instabilities. Whether these traps are filled or empty does not significantly affect the 1/f noise. A detailed study of the 1/f noise, temperature dependence of charge trapping, and radiation response of these SOI nMOSFET transistors shows that charge exchange with shallow electron traps in the buried oxide occurs mostly via tunneling. Low frequency noise in the double-gate mode of device operation is also investigated, and found to help mitigate the 1/f noise in fully depleted SOI MOSFETs.

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