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Title page for ETD etd-09282016-101105

Type of Document Dissertation
Author Kiddie, Bradley Thomas
Author's Email Address bradley.t.kiddie@vanderbilt.edu
URN etd-09282016-101105
Title Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
William H. Robinson Committee Chair
Bharat L. Bhuva Committee Member
Gabor Karsai Committee Member
Mark N. Ellingham Committee Member
Ronald D. Schrimpf Committee Member
  • reliability
  • radiation
  • eda
  • single-event transient
  • single-event multiple-transient
  • placement
  • algorithm
Date of Defense 2016-09-01
Availability unrestricted
The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical charge decreases, and operating frequencies increase. In space and other harsh environments, single ion strikes are more likely to affect multiple, physically-adjacent devices on a modern IC, thereby introducing formidable research problems for (1) modeling these effects and (2) designing circuits to mitigate them. While single-event transient (SET) behavior traditionally has been well characterized, single-event multiple-transients (SEMT) require a more complex and novel approach to capture reliability characteristics with tenable simulation times prior to chip manufacturing.

This dissertation presents an automated method to quickly characterize modern combinational logic blocks for radiation-induced SEMT vulnerability. Radiation events are modeled based on physically-observed effects, and then integrated into an electronic design automation (EDA) functional verification flow for ease of implementation. When considering the placement of standard logic cells, SEMT modeling reveals the impact on charge sharing and diffusion, and consequently reliability of logic circuits in the presence of multiple transients. Modifications to standard cell placement are investigated, and a new EDA placement algorithm is developed and implemented to achieve reductions in SEMT-induced errors with zero cost to circuit area and minimal effects on other circuit performance characteristics.

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