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Title page for ETD etd-09062010-120803

Type of Document Master's Thesis
Author Benakanakere Sheshadri, Vijay
Author's Email Address vijay.b.sheshadri@vanderbilt.edu
URN etd-09062010-120803
Title Upset trends in flip-flop designs at deep submicron technologies
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Dr. Bharat L Bhuva Committee Member
Dr. Robert A Reed Committee Member
  • Critical Charge
  • DICE
  • Q8FF
  • Charge threshold plot
  • MRED
Date of Defense 2010-08-04
Availability unrestricted
Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come an undesired increase in vulnerability of flip-flops to soft errors, which are caused by energetic particles that either directly or indirectly deposit energy, and create electron-hole pairs in the semiconductor material. These charges, when collected at a circuit node, perturb the associated node voltage, creating a transient pulse, which may alter the data stored in the flip-flop, causing a single- event upset (SEU). Decreasing technology feature size has resulted in higher packing densities, as a result of which, single-event related charge might be collected at multiple nodes in a circuit. Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment using Monte-Carlo Radiative Energy Deposition (MRED) simulations for charge deposition in several technology generations.
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