Type of Document Dissertation Author Loveless, Thomas Daniel Author's Email Address email@example.com URN etd-08262009-132854 Title A generalized single-event analysis and hardening options for mixed-signal phase-locked loop circuits Degree PhD Department Electrical Engineering Advisory Committee
Advisor Name Title Lloyd W. Massengill Committee Chair Bharat L. Bhuva Committee Member Mark Ellingham Committee Member Robert A. Reed Committee Member W. Timothy Holman Committee Member Keywords
- Phase-locked loops
- Single-Event Effects
- Radiation Effects
- Single-Event Transients
- Circuit analysis
Date of Defense 2009-08-03 Availability unrestricted AbstractA reliability concern of growing interest in the microelectronics community is the deleterious effect of ionizing radiation. The so-called "single events" – single particles which can penetrate semiconductor material leaving ionized charge in their wake – can cause information corruption and transient system failure. Single events (SE) are ubiquitous – this radiation emanates from processing and packaging material integral to a circuit, as well as the environment external to a circuit. Once only the concern of space-bound systems, integrated circuit (IC) density and power scaling have propelled this issue to the forefront of reliability concerns at current technology nodes. In mixed-signal systems, the effect of an SE particle strike is the generation of a transient signal (single-event transient or SET) that competes with the legitimate signals propagating through a circuit or perturbs the functionality of the circuit. There is a particular interest in the effect of SETs on the phase-locked loop (PLL) because of the propensity to cause loss of frequency integrity, and the resultant wide-spread impact on high-performance systems.
This dissertation applies both circuit-level simulations and experimental testing to characterize SETs in a common PLL topology. The simulations and experimental procedures target the PLL sub-circuits so that individual contributions to the overall PLL SET vulnerability are distinguished and analyzed. Additionally, novel analyses are offered that effectively predict the relative contributions of SET generation within the PLL. Furthermore, the analyses are utilized to develop a generalized model for single transient propagation through the PLL.
Although this work primarily discusses PLLs in the context of on-chip clock generation and skew reduction in the presence of ionizing particles, it is the goal of this work to present a broad-spectrum model for single transient propagation through PLL topologies for a variety of applications and operating environments. The transient model is formulated from a conventional linear PLL model commonly used in a variety of noise analyses. However, the model is unique in that the resulting fundamental design equations are derived in closed-form under the assumption that transients are a result of single impulses applied to the various sub-circuits rather than continuous nondeterministic sources. This approach vastly simplifies the analysis and provides insight into the closed-loop parameters that directly influence the generation and propagation of transients through the PLL. Moreover, a novel design parameter, the ‘PLL critical time constant’, is discovered to be the fundamental factor determining the ease at which transients influence the output phase displacement. As a result, a comprehensive set of design guidelines for ‘analytical transient mitigation’ is developed and applicable to all PLL topologies subject to single transient phenomena.
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