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Title page for ETD etd-07242007-104504

Type of Document Master's Thesis
Author Sewell, George Edmond
URN etd-07242007-104504
Title Security for the processor-to-memory interface using field programmable gate arrays.
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
William H. Robinson, Ph.D. Committee Chair
Gabor Karsai, Ph.D. Committee Member
  • security on FPGAs
  • fpga
  • field-programmable gate arrays
  • Data encryption (Computer science)
Date of Defense 2007-07-19
Availability unrestricted
Trustworthy computer systems protect the access of sensitive information by an unauthorized agent (i.e., an attacker). However, security vulnerabilities exist which can allow a system to be compromised by an attacker. An attacker could simply download physical memory to recover sensitive information. Encrypting memory utilized by the processor can provide protection against this type of access, but inserting an encryption module between the processor and memory has its challenges. Proposed here is a method for viably encrypting the data channel using an FPGA between processor and memory in an effort to minimize significant redesigns for the processor. First, an overview of security on FPGAs is discussed, highlighting advantages and problems. Second, a discussion of an implementation of the DES algorithm on an FPGA is covered in depth. Next, an overview of the entire system, processor, encryption and memory, is detailed. Finally, it concludes with a discussion of the performance experiment and analysis.
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