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Title page for ETD etd-05152019-100307

Type of Document Dissertation
Author Harrington, Rachel Christine
Author's Email Address rachelquinn827@gmail.com
URN etd-05152019-100307
Title Models for Characterizing Single-Event Effects in Advanced Technology Circuits
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Lloyd Massengill Committee Chair
Bharat Bhuva Committee Member
Jeffrey Kauppila Committee Member
Marcelo Disconzi Committee Member
Michael Alles Committee Member
  • modeling
  • single-event transient
  • single-event upset
  • single-event effects
Date of Defense 2019-04-15
Availability unrestricted
At each emerging technology node, characterization of single-event transients and upsets is crucial to accurately predict soft error rates for circuits operating in radiation environments. While experimental single-event characterization is crucial for gaining knowledge about the radiation response for circuits, designing, fabricating, and testing circuits is expensive and time consuming and ultimately captures only a subset of the information needed to gain a comprehensive knowledge of single-event effects for a technology node.

Therefore, models are often developed to predict single-event behavior of circuits in the absence of data and to explore parametric sensitivity. As circuits scale to lower voltages and faster logic gate switching times, experimental characterization methods and existing single-event models are challenged. In this work, five models are given for characterizing single-event upsets and transients given that circuits operate at lower biases and faster speeds than in previous technologies.

Three of the models developed can be used to characterize single-event upsets. First, a state space model developed to analytically characterize single-event upsets in memory elements is presented. The model takes into consideration the single-event waveform shape in order to predict whether or not an upset will occur in static random access memory (SRAM). Second, a model for estimating logic SEU cross-section given experimental SET data is derived for circuits where transient widths are on the order of logic gate switching times. Third, data from irradiation of a 14/16nm flip-flop are used to develop an empirical model for predicting SEU cross-section for variation in circuit bias that incorporates an analysis of transistor sensitive area.

The other two developed models can be used to characterize single-event transients. The issue of increased circuit switching speed is addressed through a model that extracts fast single-event transients from single-event upset data. Analyses of the impact of these fast transients on single-event upset cross-sections is also presented.

Finally, an evaluation of the effect of bias variation on SETs in FinFET transistors allows circuit designers to gain insight into SET distributions from transistor drive currents.

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