Type of Document Dissertation Author Kauppila, Amy Vaughn URN etd-04092012-111410 Title Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells Degree PhD Department Electrical Engineering Advisory Committee
Advisor Name Title Dr. Bharat L. Bhuva Committee Chair Dr. Lloyd W. Massengill Committee Member Dr. Ronald D. Schrimpf Committee Member Dr. Shi-Jie Wenshwen@cisco.com Committee Member Dr. W. Timothy Holman Committee Member Keywords
- single event upset
- parameter variation
Date of Defense 2012-03-26 Availability unrestricted AbstractCurrent deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects
that affect circuits’ radiation response. For instance, decreasing device size has led to decreased storage charge and increased operating
speeds. Decreased storage charge contributes to single event sensitivity since the charge deposited by the ionized particle is now more on
par with the storage node charge. The increased operating speeds increase circuit sensitivity since they are now comparable to the speed
of a single event transient. Single events are expected to dominate other reliability concerns in deep sub-micrometer devices due to
decreased transistor currents and nodal capacitances. Thus, it is vital to understand and quantify the impact of contributing mechanisms.
In addition to the challenges presented by radiation, transistor and chip design also faces a challenge from the variations that are inherent
to the manufacturing process. During chip fabrication, extreme measures are taken to ensure precision. However, variations in lithography,
random dopant fluctuations, gate depletion, surface state charge, and line-edge roughness cause changes in individual transistor behavior
and therefore, changes in the behavior-describing transistor parameters. The non-standard behavior then affects circuit performance and
therefore impacts single event response. It is anticipated that process variations will substantially increase with shrinking device sizes.
Consequently, the potential impact of process variations on SE circuit response is significant.
In order to accurately predict the single-event response of any circuit, it is necessary to identify and quantify the impact of the specific
process variations. This work correlates the shifts in radiation response to specific device and process-parameter variations by quantifying
the impact of process variability on the range of single-event upset (SEU) critical charge. Monte-Carlo simulations are leveraged to assess
the impact of process variations on SEU response. This dissertation analyzes the impact of process variations on the single-event upset
response of sub-100nm CMOS memory storage circuits.
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