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Title page for ETD etd-04042011-192430

Type of Document Master's Thesis
Author Blaine, Raymond Wesley
URN etd-04042011-192430
Title The Design of Single-Event Hardened Bias Circuits
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
W. Timothy Holman Committee Chair
Lloyd W. Massengill Committee Co-Chair
  • single-event
  • analog
  • mixed-signal
  • radiation
Date of Defense 2011-03-11
Availability unrestricted
Bias circuits (e.g. current sources) provide essential global signals in analog and mixed-signal design. Ideally, a bias circuit should be invariant over operating conditions such as temperature, output load, and supply voltage. Given the effort and cost required to implement a high-performance precision bias current source, current mirrors are typically used to replicate a single stable current throughout an entire integrated circuit. Consequently, a single-event (SE) strike to a critical bias circuit node can have wide-ranging global effects throughout the IC. A hardened precision bias current source is essential to prevent multiple errors from disrupting the operation of an entire integrated system.

This thesis presents a novel radiation-hardened-by-design (RHBD) technique that takes advantage of the multi-node charge collection mechanism and employs it through a balancing and mirroring circuit topology to mitigate the effects of a single event strike. This technique, called sensitive node active charge cancellation (SNACC), can be applied to harden critical nodes in analog and mixed-signal circuits. In this work, the SNACC technique is applied to a bias current source topology typical of the designs used throughout industry. The hardened bias circuit is compared with a traditional capacitive hardening technique to quantify its usefulness and performance. The SNACC hardening technique is verified using simulations in a 90-nm CMOS process.

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