Type of Document Dissertation Author Maillard, Pierre Author's Email Address email@example.com URN etd-03292014-104403 Title Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits Degree PhD Department Electrical Engineering Advisory Committee
Advisor Name Title Dr. Lloyd W. Massengill Committee Chair Dr. W. Timothy Holman Committee Chair Dr. Ronald D. Schrimpf Committee Member Dr. Stephen P. Buchner Committee Member Dr. T. Daniel Loveless Committee Member Keywords
- Analog Mixed Signals
- Delay Locked Loop
- Radiation Hardening By Design
- Single Event Transients
Date of Defense 2014-01-21 Availability unrestricted AbstractThe purpose of this PhD work has been to investigate, model, test, develop and provide hardening techniques and guidelines for the mitigation of single event transients (SETs) in analog mixed-signal (AMS) delay locked loops (DLLs) for radiation-hardened applications.
Delay-locked-loops (DLLs) are circuit substructures that are present in complex ASIC and system-on-a-chip designs. These circuits are widely used in on-chip clock distribution systems to reduce clock skew, to reduce jitter noise, and to recover clock signals at regional points within a global clock distribution system. DLLs are critical to the performance of many clock distribution systems, and in turn, the overall performance of the associated integrated system; as such, complex systems often employ multiple DLLs for clock deskew and distribution tasks. In radiation environments such as on-orbit, these critical circuits represent at-risk points of malfunction for large sections of integrated circuits due to vulnerabilities to radiation-generated transients (i.e. single event transients) that fan out across the system.
The analysis of single event effects in analog DLLs has shown that each DLL sub-circuit primitive is vulnerable to single event transients. However, we have identified the voltage controlled delay line (VCDL) sub-circuit as the most sensitive to radiation-induced single event effects generating missing clock pulses that increase with the operating frequency of the circuit. This vulnerability increases with multiple instantiation of DLLs as clock distribution nodes throughout an integrated system on a chip. To our knowledge, no complete work in the rad-hard community regarding the hardening of mixed-signal DLLs against single event effects (missing pulses) has been developed. Most of the work present in the literature applies the “brute force” and well-established digital technique of triple modular redundancy (TMR) to the digital subcomponents.
We have developed two novel design techniques for the mitigation of DLL missing pulses that are fully implementable in modern CMOS technologies. These techniques offer to the community the choice of hardening using a restoring current technique in the VCDL sub-circuit to inhibit the creation of missing pulse errors, or using a combinational logic error monitoring technique to correct missing pulses after they occur in real time. We have implemented both of these techniques with minimal area and power penalties when compared to TMR. In addition, these hardening techniques have been extrapolated to other clock circuits, such as digital PLLs.
The first hardening technique uses a hardened complementary differential pair VCDL to increase the critical charge (Qcrit) necessary for single event transient generation and thus mitigate missing pulses at the source. Our implementation of this technique at 180 nm, 90 nm and 40 nm required less than a 2% area penalty over a non-hardened design. To experimentally validate this technique, hardened VCDLs were designed and fabricated in 180-nm IBM and 40-nm UMC technologies, then tested at the Naval Research Lab in Washington D.C. The second hardening technique, based on combinational logic pulse monitoring, uses an error correction circuit to mitigate the missing pulses as they occur. This ECC technique is implemented via a “peeled” VCDL (i.e. each transistor is split in area but doubled in multiplicity). We have shown the effectiveness of this technique by implementing it in a Xilinx Virtex 5 FPGA. Furthermore, this new ECC technique is independent of technology scaling – a highly valuable attribute for sub-50 nm design applications.
In addition to the formulation, simulation, prototyping, fabrication, and testing of these new hardening solutions, we developed a unique single event analytical model to guide future hardened DLL designs at advanced technology nodes. The model was furthermore generalized to PLL and DLLs. These analytical models were then used to provide a set of equations to the designer for important insight into hardening choices and tradeoffs based on design specifications, in conjunction with a broad set of guidelines for the design of hardened DLLs regarding circuit topology choices and parameter sensitivity on radiation exposure.
We are confident that these results, tools, and guidelines will significantly expand the state-of-the-art in the design of hardened DLL clocking circuits for rad-hard applications.
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