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Title page for ETD etd-03042018-174735


Type of Document Dissertation
Author Maharrey, Jeffrey Alan
Author's Email Address jamaharrey@gmail.com
URN etd-03042018-174735
Title Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Tim Holman Committee Chair
Bharat Bhuva Committee Member
Jeff Kauppila Committee Member
Lloyd Massengill Committee Member
Mark Ellingham Committee Member
Keywords
  • single event transient
  • radiation
  • rhbd
  • digital
Date of Defense 2018-02-05
Availability unrestricted
Abstract
As design choices within a single CMOS technology become ever more complex with each new technology generation, and power consumption constraints push operating voltages lower, this research provides guidance into the efficient characterization and mitigation of single-event-transients (SET) for ground-based and space-deployed applications exposed to harsh radiation environments.

This research experimentally shows that as supply voltage decreases towards near-threshold voltages, SET duration and electrical propagation delay scale in a similar manner. Although similar in trend, SET duration and electrical delay are shown to be linked to supply voltage through different physical processes. The implication of these trends is reassuring for the use of filter-based hardening techniques at near-threshold voltages. Additionally, data show an increase in the sensitive area of logic gates as supply voltage decreases. Due to the increase in sensitive area at reduced supply voltages, filters designed for nominal supply voltage operations will not be as effective at reduced supply voltages.

Lastly, a technology-agnostic rad-hard-by-design combinational logic topology, Dual Interlocked Logic (DIL), was developed and is shown to be resilient to SET propagation even for multi-node strikes. The topology was validated via simulation with the latest bias-dependent SEE model available and via a 16nm/14nm bulk finFET TCV exposed to heavy-ion broadbeam. Similar to cascode voltage switch logic (CVSL) in form, DIL offers increased SET resiliency while still maintaining the fast characteristic switching times of modern CVSL circuits. Compared to traditional triple modular redundancy (TMR) based SET hardening approaches, DIL offers a beneficial tradeoff in area, power and portability. Additionally, the dual-differential input/output configuration of DIL also gives it the unique ability to naturally integrate alongside differential DICE flip-flops, commonly found in rad-hard design libraries, to create a single-node-robust synchronous digital system capable of implementing any arbitrary digital function.

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