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Title page for ETD etd-02242011-141755

Type of Document Master's Thesis
Author Dick, Kevin Douglas
Author's Email Address kevin.dick@vanderbilt.edu
URN etd-02242011-141755
Title Fault de-interleaving for reliability in high-speed circuits
Degree Master of Engineering
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Jeffrey D. Black Committee Member
William H. Robinson Committee Member
  • de-interleaving
  • parallel multiplier
  • serial multiplier
  • Spurious-Free dynamic range
  • interleaving
Date of Defense 2010-12-15
Availability unrestricted
The majority of modeling and simulation of single event transients (SETs) and their effects is normally done at a transistor level, known as micro-modeling. These simulations give insight into how a transistor will behave when struck by SETs. The micro-modeling of single-particle effects in Integrated Circuit (IC) devices can simulate charge collection, charge deposition/generation and ionic interaction with the semiconductor material. Micro-modeling works very well on a small circuit, when there are a low number of transistors. However, modeling large circuits on a transistor level can be time- and cost-consuming. System-level modeling and simulation allow for large circuits to be simulated in less time and less cost. Under the correct conditions, the results of macro-modeling (system-level) can approximate the results of micro-modeling.

This thesis focuses on the simulation of SETs that last longer than one clock cycle from a macro-modeling perspective. Simulating the SETs is done through the transient fault injection method. Transient fault injection is the method of injecting a fault on a certain node and observing what happens as it propagates through the circuit. It discusses the design and simulation of both a 4x4 serial full adder implemented multiplier and a 4x4 parallel full adder implemented multiplier. The burst error mitigation approaches used in communication theory are discussed and compared with the results of the multipliers. The results are compared for SETs of clock cycle lengths 1, 6 and 36 that are applied to all the nodes for a 16x16 serial full adder implemented multiplier and a 16x16 parallel full adder implemented multiplier. A frequency analysis is presented for the both multipliers with no SETs, a SET of length 6 and a SET of length 36.

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