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Title page for ETD etd-11302012-110113


Type of Document Dissertation
Author Limbrick, Daniel Brian
Author's Email Address Daniel.B.Limbrick@Vanderbilt.Edu
URN etd-11302012-110113
Title Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Dr. William H. Robinson Committee Chair
Dr. Bharat Bhuva Committee Member
Dr. Gabor Karsai Committee Member
Dr. Lloyd Massengill Committee Member
Dr. Mark Ellingham Committee Member
Keywords
  • reliability-aware synthesis
  • single event transient
  • pulse width
  • combinational logic
  • soft error
  • logic synthesis
Date of Defense 2012-09-13
Availability unrestricted
Abstract
Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements of a digital system, but also include vulnerabilities in the combinational logic. Reliability-aware synthesis has emerged as a method to mitigate the effects of soft errors in combinational logic. Few studies have focused on the inherent impact that logic synthesis algorithms have on circuit topology, and therefore reliability. This dissertation investigates the impact that area and delay optimizations, computational effort, and standard cell availability have on the error propagation probability of individual circuit nodes. Additionally, this work identifies circuit characteristics that can be used during synthesis that help in choosing the most reliable circuit implementation. Finally, an approach to minimize circuit vulnerability based on cell selection is introduced.

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