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Title page for ETD etd-04082011-122234


Type of Document Master's Thesis
Author Toomey, Corey Thomas
Author's Email Address corey.t.toomey@gmail.com
URN etd-04082011-122234
Title Statistical fault injection and analysis at the register transfer level using the Verilog procedural interface
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Bharat Bhuva Committee Chair
William H. Robinson Committee Member
Keywords
  • Register Transfer Level
  • Fault Injection
  • Architectural Vulnerability Factor
  • Soft Errors
  • Single Event
  • Verilog Procedural Interface
  • Statistical Fault Injection
Date of Defense 2010-08-05
Availability unrestricted
Abstract
Soft errors are becoming an increasingly important issue in today’s microelectronics industry. With decreasing transistor sizes and increasing transistor counts, it is simply not efficient to harden every circuit module against soft errors. Thus a designer must selectively harden the most vulnerable modules of a design. This thesis addresses the need for a non-invasive, portable, and easy to use software tool for determining the architectural-vulnerability factor (AVF) of a given design and its sub-modules. Fault injection and analysis is carried out at the register-transfer level to cut down on simulation time and simulation space. The Verilog-procedural interface (VPI) is used to implement the fault injection and error detection. Testing has been carried out on an ASIC design with 1.1 million flip-flops and an eight-bit microprocessor. Simulation results for 1,500 runs of the ASIC and 50,000 runs of the microprocessor are used to estimate AVF for the designs and their sub-modules. Other relevant results to help determine the vulnerability of a circuit module, such as error latency, benign errors, and silent errors, are also evaluated. A designer can then use this data to select the most vulnerable sub-modules or architectural structures of a design for hardening against soft errors.
Files
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