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Title page for ETD etd-03252012-195135


Type of Document Master's Thesis
Author Chatterjee, Indranil
Author's Email Address indranil.chatterjee@vanderbilt.edu
URN etd-03252012-195135
Title Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Bharat L. Bhuva Committee Chair
Ronald D. Schrimpf Committee Member
Keywords
  • Soft-errors
  • Single-Event Upset Reversal
  • Heavy Ion Irradiation
  • Triple-well
  • Dual-well
  • Single-Event Effects
Date of Defense 2012-03-02
Availability unrestricted
Abstract
CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This work presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the “Single Event Upset Reversal” mechanism that reduces sensitivity at high LETs.
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