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Title page for ETD etd-03242014-215625


Type of Document Master's Thesis
Author Chen, Yanran
Author's Email Address yanran.chen@vanderbilt.edu
URN etd-03242014-215625
Title Single-event characterization of digitally controlled oscillators (DCOS)
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Lloyd W. Massengill Committee Chair
Thomas D. Loveless Committee Member
Keywords
  • SEEs
  • ADPLLs
  • DCOs
Date of Defense 2014-02-04
Availability unrestricted
Abstract
Single-event effects (SEEs) in Digitally Controlled Oscillators (DCOs) are characterized in this work. Single-event strikes happening in the flipflops (FFs) of the registers of the DCOs would lead to oscillating frequency errors. Single-event strikes in actual oscillator part of the circuit would result in duty cycle, missing pulse errors, or harmonic errors. Overall single event performance of the DCOs is not severely dependent on the fine-tuning topologies of the DCOs. Though previously undocumented, SE Harmonic errors exhibit longer-lasting frequency changing effects on the clock signal comparing with SE duty cycle or missing pulse errors.

SE harmonic errors are errors where multiple transitions show up in a clock cycle in- duced by SETs. We propose the accumulated phase error metric to quantify the characterized SE harmonic error. Circuit simulations show that SE harmonic error can induce up to 60π radians of accumulated phase error over 8.5 ns in a 40-nm DCO operating at 2.97 GHz. The large accumulated phase error could potentially cause an ADPLL to go out of lock for up to 8.5ns corrupting data in all systems dependent on the DCO. The lower limit of SET pulse widths to generate SE harmonic error is the largest gate’s propagation delay in the ring and the upper limit of the pulse width is the total loop delay of the DCO subtracted by the largest gate’s propagation delay in the ring. The lower and upper limits of SET pulse widths in a 40-nm DCO correspond to collected charge range of 25 fC to 335 fC (defined as collected charge window). The harmonic error mechanism is validated with both Spectre simulation results of a 40-nm DCO and electrical testing on ring oscillators composed of discrete components with FPGA performing error injection. By making the fine-tuning cell have a propagation delay of over 1/3 of the total loop delay could effectively eliminate the existence of harmonic errors.

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