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Title page for ETD etd-03162017-144405


Type of Document Dissertation
Author Gaspard, Nelson Joseph III
URN etd-03162017-144405
Title Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Bharat L. Bhuva Committee Co-Chair
W. Timothy Holman Committee Co-Chair
Lloyd W. Massengill Committee Member
Robert A. Reed Committee Member
Shi-Jie Wen Committee Member
T. Daniel Loveless Committee Member
Keywords
  • single event upset
  • CMOS
  • flip-flop
  • soft error
Date of Defense 2016-02-11
Availability unrestricted
Abstract
Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop designs. Trends show that at any LET value soft flip-flops show a decreasing single-event upset cross section with decreasing feature size. Hardened redundant storage node flip-flops show similar cross sections across technologies if the redundant storage node transistor spacing is held constant. Technology computer aided design (TCAD) simulations are used to show there are many competing mechanisms that influence flip-flip single-event upset cross sections as technology feature sizes decrease.
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