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Title page for ETD etd-01292008-150433


Type of Document Master's Thesis
Author Loveless, Thomas Daniel
Author's Email Address daniel.loveless@gmail.com
URN etd-01292008-150433
Title A radiation-hardened-by-design charge pump for phase-locked loop circuits
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Dr. Lloyd Massengill Committee Chair
Dr. Bharat Bhuva Committee Member
Keywords
  • charge pump
  • single-event transients
  • radiation-hardened-by-design
  • phase-locked loop
Date of Defense 2007-03-16
Availability unrestricted
Abstract
Single-event transients (SETs) due to terrestrial or space radiation exposure have become a growing concern in modern high-speed analog and mixed-signal electronics. Recent work with computer circuit-level simulation techniques has enabled the understanding of SET effects in mixed-signal and radio-frequency (RF) applications such as the phase-locked loop (PLL). Furthermore, a PLL radiation sensitivity weak point has been identified as the conventional current-based charge pump (CP), with ion strikes in the CP resulting in at least two orders of magnitude higher output phase displacement than any other module within the PLL.


This thesis presents a CP topology as a novel method to solving this critical SET problem with the potential of significantly improving overall PLL resistance to SET effects. A method of PLL design employing a tri-state, voltage-based charge pump (V-CP) circuit has been implemented that significantly hardens the PLL to SET effects. Simulations and experimental testing have been performed on PLL circuits designed and fabricated in the IBM 130nm CMRF8RF CMOS technology available through the MOSIS foundry system. Analysis of the measured PLL output error signatures is used to quantify the relative hardness of PLL circuits implementing a V-CP stage over a conventional CP module, demonstrating a maximum of 2.3 orders of magnitude improvement in the SET response. The design effectively eliminates the charge pump as the most susceptible element in the PLL; as a result, this hardened design technique, which can be applied to other PLL topologies, provides SE performance that is orders of magnitude better than typical PLL designs.

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